The communications and computer industries are rapidly changing to adjust to emerging technologies and ever increasing customer demand for systems with increased performance. Note, nothing described or referenced in this document is admitted as prior art to this application unless explicitly so stated.
DRAM (Dynamic Random Access Memory) and some other types of memory chips require that internal memory cells be “refreshed” periodically to prevent loss of stored data. These “refresh cycles” consume what would otherwise be useful bandwidth to the memory itself, and are typically a major issue in designing a memory chip as each used memory cell must be refreshed within a certain small amount of time or its data will be lost.
DRAM devices are typically internally composed of “banks” of memory that behave somewhat independently. Generally, a bank can be in one of four states: idle, performing a read operation, performing a write operation, or performing a refresh operation. It is important for system chips to “schedule” a sequence in which banks are read, written, or refreshed, such that a particular memory bank is not in a refresh cycle when it is desired to be read from, or written to, resulting in delay. During a command cycle, a DRAM device receives one command (e.g., refresh command, write command, read command, or NOP/idle).
Commonly, refresh cycles are initiated by system devices communicating with the DRAM devices over the communication interface between the system device and the DRAM device, by specifying a bank to refresh, and control logic within the memory chip refreshes a next set of one or more memory cells automatically. Therefore, by supplying successive refresh commands for a particular bank (typically interspersed with refresh commands for other banks, NOP, read and/or write commands), the memory locations in the particular bank are sequenced through and refreshed.